FIELD OF THE INVENTION
The invention relates to a phase-locked loop configuration having a phase detector to which a reference signal and an input signal conducted through a controllable delay device, are applied, a controller connected downstream of the phase detector for controlling the load path of at least one field effect transistor in the delay device, the load path being connected transversely to the signal path through a (respective) capacitor, and at least one inverter in the signal path of the delay device.
Such a phase-locked loop configuration is known, for instance, from an article by M. G. Johnson and E. L. Hudson, entitled "A Variable Delay Line PLL for CPU-Coprocessor Synchronization" in IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, October 1988, and is discussed therein with a view toward using it for synchronizing two processors. When two processors, such as a central processing unit and a coprocessor, are operated on one bus, production-dictated phase shifts in the equal-frequency signal clock pulses of the two processors relative to one another often arise, which at the least hinder both in achieving regulated bus access. In order to synchronize the two signal clock pulses, phase-locked loops are proposed, which have a controllable delay device instead of a controlled oscillator circuit.
In the aforementioned article, two different types of delay devices are compared with one another for that purpose. One is a circuit with an inverter, having a supply current which is reduced by means of field effect transistors as a function of a control voltage, and the other is the circuit that was already mentioned at the outset, having a serial RC member formed of a capacitor and the load path of a field effect transistor. The time constant of the RC member is variable by means of the control voltage. The inverter circuit is distinguished by a wide delay range, but is very inaccurate. In comparison, the circuit with the RC member is substantially more favorable. On the other hand, its delay range is quite limited. In order to nevertheless achieve a wide delay range and high accuracy, it is proposed that a plurality of circuits with RC members be connected in series, with inverters disposed between them. The disadvantage then, however, is that a relatively high number of individual circuits is required to achieve an adequate delay range. However that means that numerous capacitors are required, which take up a very large amount of surface area in integration.